Buffer Design and Assignment Algorithm for Structured ASIC Optimization

In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and extract the technology-dependent parameters for evaluation. Furthermore, we propose post-routing channel migration techniques, which employ intra-channel migration and inter-channel migration, to deal with the sub-channel saturation problem during buffer assignment. Compared to the baseline designs with 4X-buffer at the CLB output, our proposed structured ASIC design and optimization techniques improve the circuit performance by 65.7% and the ratio of wire delay to gate delay from 8.2 to 0.8.